AltiumEDAHigh-Speed

Altium Workflow for NVLink-Grade PCB Designs: From Stackup to Test

UUnknown

2026-02-18

11 min read

Altium‑focused workflow for NVLink‑grade PCB channels: stackup, diff‑pair tuning, simulation, and lab test plan for 2026 high‑speed designs.

Hook: Why NVLink‑grade interconnects matter for Altium‑centric NVLink‑grade interconnects

Designing PCB channels that will carry NVLink‑style high‑speed interconnects is no longer an academic exercise—it's a production requirement for AI and HPC platforms in 2026. Engineers and teams face steep signal‑integrity, manufacturability, and verification hurdles: tight impedance control, multi‑GHz loss budgets, skew and latency constraints, and rigorous test plans. This guide gives a practical, Altium‑centric, step‑by‑step workflow—from stackup to verification—so you can deliver boards that meet NVLink‑grade performance and remain manufacturable.

What this guide covers (at a glance)

Requirements and constraints for NVLink‑like channels in 2026
Designing the board stackup with Altium Designer Layer Stack Manager
Pre‑layout modeling and channel simulation strategy
Altium differential pair routing and tuning best practices
Post‑layout simulation and IBIS/IBIS‑AMI / S‑parameter workflow
Test plan: TDR, VNA S‑parameters, BERT, and manufacturing checks

1. Context and requirements (2026 trends you must account for)

Recent industry moves—like SiFive integrating NVIDIA's NVLink Fusion infrastructure into RISC‑V platforms—make NVLink‑class interconnects an increasingly common spec for chip‑to‑chip fabrics in 2025–2026. That means many PCB channels will need to support multi‑tens to hundreds of Gbps aggregate throughput, low deterministic latency, and robust error rates.

Translate these system needs into PCB constraints:

Target differential impedance: typically 85–110 Ω differential depending on PHY. Always confirm with the SerDes vendor; your Altium rules should be parametrized for ranges.
Insertion loss budget: control trace loss, dielectric loss tangent, and copper roughness to meet eye opening at the receiver.
Channel length & skew: set max pair skew budgets (ps) and per‑pair length matching rules.
Return path integrity: continuous reference plane(s) for high‑speed pairs, stitch vias near split planes.
Manufacturability: via design (backdrill, blind/buried, via‑in‑pad), finish (ENIG/Chem‑Ni/Au), and control of surface roughness. Consider lab and equipment costs when planning prototypes (compare workstation and bench kit options to keep prototype costs down — see a workstation kit guide).

2. Stackup strategy using Altium Layer Stack Manager

Start stackup design early. In Altium Designer, use the Layer Stack Manager to capture physical layer geometry and electrical properties (thickness, material, Dk, Df, copper roughness). Do not leave stackup decisions to PCB fabrication alone: they directly affect impedance and loss.

Recommended stackup template for NVLink‑grade channels (example)

This is a practical 12‑layer template that balances routing, controlled impedance, and power distribution. Adjust materials per your fab capability.

Top: signal (microstrip) — critical connector I/O
L2: plane — ground reference for top
Inner1 (L3): high‑speed stripline — differential pairs
Inner2 (L4): plane — continuous reference
Inner3 (L5): signal — routing and power
Inner4 (L6): plane — PDN
Inner5 (L7): signal — secondary high speed
Inner6 (L8): plane — return
Inner7 (L9): signal — breakout
Inner8 (L10): plane — power/return
L11: plane — return for bottom
Bottom: signal (microstrip)

Key stackup decisions:

Use striplines for the highest‑speed differential pairs when possible—inner striplines provide better return continuity and lower EMI than microstrips.
Keep continuous plane layers adjacent to signal layers to constrain fields and simplify impedance control.
Material selection: for extremely low loss target Megtron or Rogers/Isola low‑loss laminates (e.g., Isola FR408HR, Megtron 6, Rogers 3000 series) reduce dielectric loss. For many boards, a high‑grade FR‑4 (low Df) plus controlled copper roughness is a cost/benefit sweet spot.
Document Dk/Df and copper roughness in Altium for each dielectric — these parameters feed impedance calculators and S‑parameter extractions.

3. Pre‑layout modeling and simulations

Before pushing routing, validate your stackup and channel with modeling. Altium's Layer Stack Manager and impedance calculators give quick numbers, but for NVLink‑grade channels you need a chain that includes IBIS/IBIS‑AMI modeling and S‑parameter or 3D EM extraction.

Practical pre‑layout workflow

Capture PHY/SerDes electrical models: IBIS and IBIS‑AMI models for drivers/receivers from silicon vendors. Put these into your simulation library.
Define a representative channel (connector + cable/flex if used + PCB channel segments). Keep the model simple but representative.
Run a channel simulation using a channel simulator that supports IBIS‑AMI. Altium's Signal Integrity extension can do basic transient and TDR; for full IBIS‑AMI channel analysis, export to Keysight ADS, Ansys HFSS/Siwave, or a dedicated channel simulator (many teams use Keysight or Ansys for final validation).
Compute expected S‑parameter performance and insertion loss. Use the stackup to estimate 1‑gamma conductor/dielectric losses and approximate copper roughness impact. If you need a bench setup for measurements, follow basic lab-build guides to equip a low‑cost bench (see a compact tech kit overview guide).
Iterate the stackup until insertion loss at the Nyquist frequency (or Nyquist of the highest lane rate) meets the PHY receiver equalization capability.

4. Implementing design rules in Altium (essential rule sets)

Encoding rules into Altium early prevents rework. Use the PCB Rules and Constraints Editor to lock in electrical and manufacturing constraints.

Impedance rules: Create Differential Pair Width/Gaps tied to the stackup. For example, a 100 Ω differential target with ±5% tolerance. In Altium, set this under the Design » Rules » Electrical » Routing » Differential Pairs.
Length/match rules: Use Length Tuning and Maximum Skew rules (ps or mm). Set per net class (e.g., NVLINK_Pairs).
Return path and via rules: Enforce via stitching density and min/max via annular ring. Define backdrill requirements as manufacturing notes.
Clearance and spacing: Tight spacing between adjacent high‑speed pairs raises crosstalk; create routing classes with spacing rules that balance density and performance.
Controlled impedance verification: Add a rule to flag impedance mismatches beyond tolerance; run continuous checks during routing.

5. Differential pair routing and tuning in Altium

Routing differential pairs for NVLink‑like channels is where disciplined engineering meets routing craft. Altium provides interactive differential pair routing, automatic length tuning, and real‑time rule checking—use them aggressively.

Best‑practice routing steps

Assign nets to a dedicated high‑speed net class before routing.
Use the Interactive Differential Pair router in Altium for controlled separation. Lock pair orientation to minimize skew from via staggering.
Prefer short microstrip runs only for connector breakout; keep long runs in inner striplines where possible.
Minimize layer transitions. Each via adds discontinuity and needs backdrill; when unavoidable, use backdrilling and specify non‑plated through via (NPTH) or plugged vias for via‑in‑pad.
Place ground via fences adjacent to connectors and along pair runs when crossing splits; stitch ground plane on both sides of the differential pair transitions.
Use Altium's length tuning feature to meet per‑pair length match. Remember: tuning by meander increases loss and resonances—tune conservatively and prefer symmetric tuning across pairs.
Keep crosstalk in check by maintaining spacing to adjacent aggressors; where density forces proximity, simulate worst‑case aggressor scenarios.

Practical Altium knobs

Set the Differential Pair Width/Gaps in your net class and enable continuous impedance checking.
Enable online rule checking (DRC) to catch violations while routing.
Use interactive busing to route multi‑lane interfaces efficiently while preserving pair topology.

6. Post‑layout verification and advanced simulation

Once routing is complete, you must verify: S‑parameters, channel eye diagrams, and PDN behavior. Altium can export the physical geometry to third‑party SI/EM tools and generate test coupons for the fab.

Post‑layout workflow

Export the routed channel (route polygons, vias) as ODB++ or IPC‑2581 for EM/SI tools. Most advanced SI tools accept these exports for 2.5D/3D extraction.
Generate S‑parameters via 2.5D solvers (for long structures) or 3D EM (for connectors and complex transitions). Tools commonly used: Ansys HFSS/Siwave, Keysight ADS/HFSS, or Cadence Sigrity. If you need tips for building a basic measurement bench and scope setup or choosing a monitor/bench display, see an equipment roundup like this guide.
Run IBIS‑AMI channel simulations with the manufactured S‑parameters and PHY models. Check BER predictions, eyes, and required equalization taps.
Perform time‑domain reflectometry (TDR) simulation to locate impedance discontinuities and validate via transitions and connector regions.
Run PDN impedance analysis (Altium has PDN analysis extensions; for deep analysis use Ansys or Keysight) to ensure supply rails meet decoupling targets at frequencies relevant to PHY equalizers and clock circuits.

7. Test plan creation (what to measure and how)

A thorough test plan reduces respins. Define tests that map directly to your channel requirements. Below is a practical lab test plan suitable for production validation and R&D.

Essential test cases

S‑parameter sweep (VNA): Measure S11/S21 to the system bandwidth. Compare to simulated S‑parameters and insertion loss budgets. Calibrate to board ports with calibration standards on the board (SOLT or TRL as appropriate).
TDR/TDT: Locate impedance discontinuities near connectors and vias. Use a high‑bandwidth oscilloscope/TDR instrument with a calibrated probe.
BERT / Eye diagram: Perform bit error rate tests using a BERT or the PHY's built‑in test mode. Record BER at target rates and margins, and capture eye height/width under typical stress conditions (temperature, supply variations).
Jitter decomposition: Measure deterministic and random jitter contributions. Use a phase noise analyzer or high‑speed scope with jitter toolkit.
Cross‑talk and aggressive channel tests: Stimulate adjacent lanes to verify crosstalk impact. Use worst‑case aggressor patterns during BERT runs.
PDN noise and switching events: Measure PDN impedance across frequency using a VNA and compare to decoupling target curves. Use near‑field probes to find local hot spots.
Thermal / reliability stress: Run thermal cycling and high‑temperature operation tests to validate solder joints and materials (e.g., ENIG vs. HASL behavior for high‑speed contacts).

Test coupon and manufacturing checks

Include dedicated test coupons on the PCB panel to validate controlled impedance and signal behavior independent of the system board:

90 mm single pair coupon for impedance measurement (microstrip & stripline sections)
Connector transition coupon with mating connector and shorted plane
Stitched plane coupon to validate via stitching density
Material stackup coupon to verify Dk/Df and copper roughness — include detailed field test guidance or a field review style checklist for panel verification

8. Manufacturing notes and DFM checklist

Communicate constraints to your fabricator and assembler up front. Include these in the fabrication notes using Altium's ECO/Notes and the mechanical drawing package.

Specify controlled impedance tolerance (e.g., 100 Ω ±5%), target copper roughness Ra, and dielectric Dk/Df.
Call out via backdrill depth, via fill (copper or epoxy) for via‑in‑pad, and plug requirements.
Define plating and finish: ENIG is common for high‑speed connectors; be explicit about surface treatment.
Specify panelization, coupon placement, and test pad locations for automated probing.
Request manufacturer process capability data (Cp/Cpk) for impedance control and layer thickness variation.

9. Common pitfalls and how to avoid them

Late stackup changes: Lock stackup early. Changing layer thickness after routing invalidates impedance and may force rework.
Over‑meandering: Excessive serpentine tuning increases dielectric loss and can create resonances; prefer symmetric length matching and minimize meanders.
Neglecting plane splits: Splits under high‑speed pairs kill return continuity—rearrange planes or move pairs to another layer.
Under‑specifying finish/copper roughness: It can add dB loss at high freq. Quantify these with the fabricator and include in simulations.
Relying on only Altium for advanced SI: For NVLink‑class rates, plan to export to Ansys or Keysight for final channel verification.

10. Example iteration case: from first‑pass board to validated channel

Here is a condensed, real‑world style iteration you can replicate:

Create a 12‑layer stackup in Altium with inner striplines for the primary NVLink lanes using Megtron/FR408HR parameters.
Define net class NVLINK_LANE with differential target 100 Ω ±5% and length match ±50 ps.
Route lanes interactively, limit via transitions to connector breakout, and add ground stitching near connectors.
Export ODB++ and run a 2.5D extraction in Keysight ADS to get S‑parameters. Simulate IBIS‑AMI channel; the eye margin is marginal at highest rate.
Tweak stackup (reduce dielectric thickness adjacent to stripline layer, switch to lower Df laminate) and re‑run extraction—S21 improves by ~0.7 dB at target freq.
Order a small prototype panel with impedance coupons and backdrilled vias. Measure S‑parameters on board—compare to simulation within expected tolerances. Run BERT tests to confirm BER < target (e.g., 1e‑15) at operational conditions.

Actionable takeaways

Start stackup design in Altium immediately and document Dk/Df and copper roughness for every dielectric.
Encode differential impedance, length, skew, and via rules in Altium net classes before routing.
Use Altium for layout discipline but plan to export to Ansys/Keysight for final IBIS‑AMI and S‑parameter‑based channel validation.
Create targeted test coupons and a lab test plan (VNA, TDR, BERT) to validate your manufactured boards against simulations.
Lock manufacturing requirements (backdrill, via fill, finish) with your fabricator and include Cp/Cpk expectations for impedance control.

Future outlook: 2026 and beyond

As NVLink Fusion and similar fabrics proliferate across heterogeneous compute (including RISC‑V + GPU pairings), PCBs will increasingly be required to carry ever higher aggregated bandwidths. Expect these trends through 2026:

Greater demand for early co‑simulation: EDA + EM coupling early in the design cycle. See a practical guide to hybrid/edge orchestration and distributed workflows that benefit from early coupling.
Wider adoption of advanced low‑loss laminates and tighter fab process controls to meet loss budgets.
More automation in EDA workflows: built‑in IBIS‑AMI tools and smoother handoff between Altium and commercial SI/EM tools.
Stronger emphasis on manufacturability: embedded test coupons, more precise surface finish specs, and standardized test fixtures for BERT/VNA labs.

“Design for signal integrity is design for manufacturability.”

Final checklist before tape‑out (quick reference)

Stackup documented in Altium with Dk/Df and copper roughness.
Impedance and differential routing rules encoded and verified.
Via and backdrill rules in place and noted on fabrication drawings.
Exported channel geometry for S‑parameter extraction and IBIS‑AMI simulation.
Test coupons included on panel; assembly/test fixture requirements specified.
PDN decoupling plan validated; thermal budgets checked.

Call to action

If you're designing NVLink‑grade channels in Altium now, start your next project by exporting a stackup and net class template from this article's checklist and run an early channel simulation. Need a hands‑on walkthrough integrating Altium with Ansys or Keysight workflows, or a review of your stackup and test plan? Contact our circuits.pro experts for a pre‑tape‑out review and template package tailored to NVLink‑class interconnects.

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